Interrupt Request Compressor - Infineon Technologies TC1728 User Manual

19.1.5.5 Interrupt Request Compressor

The interrupt control logic of the MSC uses an interrupt compressing scheme that allows
high flexibility in interrupt processing. Each of the four interrupt sources can be directed
via a 2-bit interrupt node pointer to one of the four service request outputs SR[3:0]. This
also makes it possible to connect more than one interrupt source to one interrupt output
SRx.
Data Frame
Interrupt
Command
Frame Interrupt
Time Frame
Interrupt
Receive Data
Interrupt
Figure 19-27 MSC Interrupt Request Compressor
Note: The number of available MSC interrupt outputs depends on the implementation of
the MSC module(s) in the specific product (see
User's Manual
MSC, V1.37 2009-05
ICR
EDIP
2
00
EDI 01
10
11
ICR
ECIP
2
00
ECI
01
10
11
ICR
TFIP
2
00
TFI
01
10
11
ICR
RDIP
2
00
RDI 01
10
11
19-35
Micro Second Channel (MSC)
≥1
Service
Request
Output
SR0
≥1
Service
Request
Output
SR1
≥1
Service
Request
Output
SR2
≥1
Service
Request
Output
SR3
MCA06253
Page 19-72 for TC1728 details).
TC1728
V1.0, 2011-12