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The Downstream Control Register is used to control the operation mode and frame
layout of the downstream channel transmission. It also contains the two pending status
bits.
DSC
Downstream Control Register
31
30
29
28
0
r
15
14
13
12
EN
EN
DS
SEL
SEL
DIS
H
L
rh
rw
rw
Field
Bits
TM
0
CP
1
DP
2
User's Manual
MSC, V1.37 2009-05
(14
27
26
25
24
PPD
rw
11
10
9
8
NDBH
rw
Type Description
rw
Transmission Mode
This bit selects the transmission mode of the
downstream channel.
0
Triggered Mode selected
B
1
Data Repetition Mode selected
B
rh
Command Pending
This bit is set when the downstream command register
DC is written. CP is cleared when the first bit of the
related command frame is sent out.
rh
Data Pending
In Triggered Mode, this bit is set when the set data
pending bit ISC.SDP is set by software. In Data
Repetition Mode, this bit is set by hardware at the last
passive time frame. At the start of the data frame, DP is
cleared by hardware.
19-41
Micro Second Channel (MSC)
)
Reset Value: 0000 0000
H
23
22
21
20
0
r
7
6
5
4
NDBL
rw
TC1728
19
18
17
16
NBC
rw
3
2
1
0
DP
CP
TM
rh
rh
rw
V1.0, 2011-12
H
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