Interrupt Control Registers - Infineon Technologies TC1728 User Manual

19.3.6

Interrupt Control Registers

In the TC172x, the two service request outputs SR[1:0] of the MSC0 module are
connected to one interrupt node. The upper two service request outputs SR[3:2] of the
MSC0 module are not connected to interrupt nodes, but can be used as DMA requests
(see Table 19-11).
MSC0_SRCx (x = 0-1)
MSC0 Service Request Control Register x
31 30 29 28
15 14 13 12
SET CLR
SRR SRE
R R
w w rh rw
Field Bits
SRPN [7:0]
TOS 10
SRE 12
SRR 13
CLRR 14
SETR 15
0 [9:8], 11,
[31:16]
User's Manual
MSC, V1.37 2009-05
(FC
27 26 25 24
11 10 9 8
0 TOS 0
r rw r
Type Description
rw Service Request Priority Number
rw Type of Service Control
rw Service Request Enable
rh Service Request Flag
w Request Clear Bit
w Request Set Bit
r Reserved
Read as 0; should be written with 0.
19-72
Micro Second Channel (MSC)
-x*4 )
H H
23 22 21
0
r
7 6 5
TC1728
Reset Value: 0000 0000
20 19 18 17
4 3 2 1
SRPN
rw
V1.0, 2011-12
H
16
0