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16.2.1
TriCore CPU OCDS Level 1
This section describes the basic features of the TriCore OCDS Level 1 hardware. For
more details please refer to the "TriCore Core Architecture V1.3.1" manual.
Features
•
Single-step support by hardware
•
Up to 4 programmable hardware breakpoints. Each one can be defined as a
combination of program counter and data address:
– Breaks on program counter (PC) value
Two precise PC values or one PC range
Break before make (BBM) possible
– Breaks on data address
Two precise data addresses or one data address range
No break before make possible (due to pipelined architecture)
– Combinations of the above break conditions
•
Suspend features
– Core Suspend-Out to suspend bus
– Configurable Core Suspend-In
•
Real-time features
– Read and write of memory/registers independent of CPU, with minimum intrusion
(stealing bus cycles by Cerberus)
– High-priority requests can still be serviced when the core is in emulation mode - by
interrupting the monitor program
16.2.1.1 Basic Concept
The TriCore CPU in the TC1728 provides OCDS with the following two basic parts:
•
Debug Event Trigger Generation
•
Debug Event Trigger Processing
The first part controls the generation of debug events and the second part controls what
actions are taken when a debug event is generated.
User's Manual
OCDS, V1.5
On-Chip Debug Support (OCDS)
16-6
TC1728
V1.0, 2011-12
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