Infineon Technologies TC1728 User Manual page 1087

Field Bits
FHT_STS 0
OVF_STS 1
UDF_STS 2
0 [31:3]
FMSTS is used to log the status of the interrupt source(s). The bits are set to 1 by
hardware. To clear a status bit the software must write a 0 at the bit position
corresponding to be bit to be cleared (writing a 1 per software has no effect on the status
bits). If software writes a 0 to a status bit that is already cleared and in the same cycle
the hardware wants to set the bit, the hardware has priority over the software.
FMTH
Fifo Monitor: Fullness Threshold Register
31
User's Manual
BMU, V2.6
Type Description
rwh Status Flag for Fifo High Threshold interrupt
0 No interrupt pending
B
1 Event related to High Threshold monitoring has
B
been detected. The event leads to an interrupt if
FMCTL.FHT_INT = 1.
rwh Status Flag for Overrun interrupt
0 No interrupt pending
B
1 Event related to overflow monitoring has been
B
detected. The event leads to an interrupt if
FMCTL.OVF_INT = 1.
rwh Status Flag for Underflow interrupt
0 No interrupt pending
B
1 Event related to underflow monitoring has been
B
detected. The event leads to an interrupt if
FMCTL.UDF_INT = 1.
r reserved bit fields. A write has no effect. Returns 0s on
read.
(48
0
r
15-43
Bus Monitor Unit (BMU)
) Reset Value: 0000 0000
H
TC1728
H
0
FHT
rw
V1.0, 2011-12