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__________________________________________________________
Device
Stepping Code/Marking
Package
This Errata Sheet describes the deviations from the current user documentation.
The module oriented classification and numbering system uses an ascending sequence over several
derivatives, including already solved deviations. So gaps inside this enumeration can occur.
This Errata Sheet applies to all temperature (SAB-/SAF-/SAK-.....) and frequency versions (.20./.40.),
unless explicitly noted otherwise.
Current Documentation
•
XC164 System Units - User's Manual V2.1, 2004-03
•
XC164 Peripheral Units - User's Manual V2.1, 2004-03
•
XC164CS Data Sheet - V2.1, 2003-06
•
C166S V2 User's Manual (Core, Instruction Set) - V1.7, 2001-01
Note:
Devices additionally marked with EES- or ES- or E followed by a 3-digit date code are
engineering samples which may not be completely tested in all functional and electrical
characteristics, therefore they should be used for evaluation only.
The specific test conditions for engineering samples are documented in a separate Status Sheet.
Contents
Section
Errata Sheet XC164CS-8F20F/40F (ES-)AD
XC164CS-8FF, -8F20F, -8F40F
ES-AD, AD
P-TQFP-100-16
- 1 of 26 -
Microcontrollers
Errata Sheet
V0.3, 2004-09-27
Mh/Es/UK, V0.3, 2004-09-27
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Related Manuals for Infineon Technologies XC164CS-8FF
Summary of Contents for Infineon Technologies XC164CS-8FF
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Page 1: Table Of Contents
Microcontrollers Errata Sheet __________________________________________________________ V0.3, 2004-09-27 Device XC164CS-8FF, -8F20F, -8F40F Stepping Code/Marking ES-AD, AD Package P-TQFP-100-16 This Errata Sheet describes the deviations from the current user documentation. The module oriented classification and numbering system uses an ascending sequence over several derivatives, including already solved deviations. -
Page 2: History List/Change Summary
1. History List/Change Summary from Errata Sheet Rev. 0.2 for XC164CS-8F devices with marking ES-AD, AD to this Errata Sheet Rev. 0.3 for XC164CS-8F devices with marking ES-AD, AD: Documentation Reference changed to XC164-16 User's Manual V2.1 (Volume 1: System Units, Volume 2: Peripheral Units), 2004-03 Description of the following problems added: Frequency Limits for Flash Read Accesses (FCPUR_X.162832): see section “Deviations from DC/AC Specification”... - Page 3 1.1 Summary of Fixed Problems (reference: device step AB) Problem Name Short Description Fixed in Step PORTS_X.009.1 Pins associated with External Bus Controller are driven after ES-AC Software Reset in Single-Chip Mode (specific description for step (ES-)AB after correction of problem PORTS_X.007)) PORTS_X.010 Sleep and Power Down Mode Supply Current influenced by P3.5 ES-AC...
- Page 4 1.3 Summary of Application Hints Name Short Description Remarks CPU_X.H1 Configuration of Registers CPUCON1 and CPUCON2 CPU_X.H2 Special Characteristics of I/O Areas steps ≥ AC FLASH_X.H1.1 Access to Flash Module after Program/Erase steps ≥ AC FLASH_X.H2.1 Access to Flash Module after Wake-Up from Sleep/Idle Mode or Shut-Down FLASH_X.H3.1 Read Access to internal Flash Module with modified Margin Level...
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Page 5: Functional Problems
2. Functional Problems EBC_X.003 TwinCAN Access with EBC enabled If the External Bus Controller (EBC) is enabled, a read or write access to the TwinCAN module fails when an external bus access with TCONCSx.PHA ≠ 00b precedes the TwinCAN access. Workaround: Since it is hard to predict the order of external bus and TwinCAN accesses (in particular when PEC transfers are involved), it is recommended to set bitfield PHA to '00' in all TCONCSx registers which... - Page 6 Workarounds (e.g. for program parts written in assembly language): generally disable overrun of pipeline bubbles by clearing bit CPUCON2.OVRUN (CPUCON2.4 = 0). This will result only in a negligible performance decrease, and will prohibit corruption of the target IP of the JMPI. provide a NOP (or any other suitable instruction) between the MUL/DIV instructions and the succeeding jump in the above cases.
- Page 7 check for long ATOMIC or EXTEND sequences, or phases where the interrupt system is temporarily disabled (e.g. by an operating system) extend the ADC conversion time (bit fields ADCTC, ADSTC) Workaround 2.1 (for standard conversions if no injected conversions are used) Use an interrupt service routine to read the results of standard conversions from register DAT.
- Page 8 Workaround 2.2 (for standard conversions if injected conversions are used in parallel) Use an interrupt service routine to read the results of standard conversions from register DAT. In the interrupt service routine, read the result register DAT twice. In case a lock situation had occurred, the second (dummy) read access will terminate the lock situation: the next conversion result #n+1 will be transferred to DAT, and interrupt request flag ADCIR will be set, such that the result #n+1 will be read correctly in the associated interrupt service routine.
- Page 9 Workaround 3 In order to avoid the problem, make sure that only one conversion is started at a time. a) For standard conversions: Instead of continuous and auto scan conversion modes, use a sequence of fixed channel single conversions which are started in the ADC conversion complete interrupt service routine (triggered by ADCIR) after the result of the previous conversion has been read from register DAT.
- Page 10 Workaround 1 In order to avoid the problem (when PLLCTRL ≠ 00b), make sure that the wake up trigger only occurs after the device has already entered sleep mode: check the RTC before entering sleep mode. If the wake up trigger will occur soon, either skip entry into sleep mode, or extend the time for the next wake up.
- Page 11 TwinCAN2.005: Double Send Under the following conditions, the problem described below will occur: Message Object X (MO , lower priority) is in the process of actually being transmitted, and then the transmit request bit for Message Object Y (MO higher priority) is set via the user software. Other message objects MO may be pending for transmission, where the priorities are MO >...
- Page 12 Simplified sample code: // Interrupt which takes place on a regular base interrupt (CC1_T0INT) void CC1_viTmr0(void) // Message Object Number ubObjNr; // for all message objects do (ubObjNr=0;ubObjNr<32;ubObjNr++) // if TxRQ is still set for MOX (CAN_HWOBJ[ubObjNr].uwMSGCTR & 0x2000) // reset TxRQ CAN_HWOBJ[ubObjNr].uwMSGCTR=0xDFFF;...
- Page 13 TwinCAN2.007: Transmit after Error During a CAN error, transmission may stop (after EOF or an error frame), until a successful reception or a write access to the TwinCAN module. Detailed Description In case of a CAN error and there is no other activity on the CAN module (e.g. frame reception / frame transmission on the other CAN node / write access to any CAN register), the transmission of messages may stop, even if some transmit requests are still set.
- Page 14 b1) 01b (VCO bypass with oscillator watchdog) if pin EA# is sampled low, and P0H.[7:5] = 000b or 011b, and ALE = low and RD# = high b2) 00b (VCO bypass without oscillator watchdog) if pin EA# is sampled low, and P0H.[7:5] = 000b or 011b, and both ALE and RD# are low b3) 11b (PLL mode) for all other combinations of P0H.[7:5] if pin EA# is sampled low Note that register SYSCON1 is only cleared after a hardware reset, therefore bit CPSYS remains at ‘1’...
- Page 15 If this failure mode has been entered, write accesses to register PLLCON have no effect. Entry into sleep mode or further internal resets (SRST or WDT reset) will not change the settings of the clock system. Also, if an oscillator fail condition or PLL unlock event occurs in this mode, the clock system will remain unchanged.
- Page 16 OCDS_X.002 OCDS indicates incorrect status after break_now requests if PSW.ILVL ≥ CMCTR.LEVEL When the OCDS processes a break_now request while the CPU priority level (in PSW.ILVL) is not lower than the OCDS break level (in CMCTR.LEVEL), the actual break is delayed until either PSW.ILVL or CMCTR.LEVEL is reprogrammed such that CMCTR.LEVEL >...
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Page 17: Deviations From Electrical And Timing Specification
3. Deviations from Electrical and Timing Specification Reference: XC164CS Data Sheet – V2.1, 2003-06 (see also Status Sheet) The following restrictions should be considered: Symbol Parameter Value TAP_X.85 Maximum ambient temperature < 85°C (SAK version only) during flash programming FCPUR X.162832 Frequency Limits for Flash Read Accesses For instruction and data read accesses to the internal flash module (including programming and erase sequences), the frequency limits listed below must be considered, otherwise instructions and operands... -
Page 18: Application Hints
The performance decrease due to an additional wait state depends on the individual characteristics of the software. Due to the internal instruction prefetch queue, the average performance decrease when using 1 wait state instead of 0 wait states is expected to be approximately 5%, and approximately 15% when using 2 wait states instead of 1 wait state. - Page 19 FLASH_X.H1.1 Access to Flash Module after Program/Erase After the last instruction of a program or erase command, the BUSY bit in register FSR is set to '1' (status = busy) after a delay of one instruction cycle. When polling the BUSY flag, one NOP or other instruction which is not evaluating the BUSY flag must be inserted after the last instruction of a program or erase command.
- Page 20 If code is executed from the internal flash after wake-up, at least 16 instructions should be executed from the internal flash before re-entering sleep/idle mode. This ensures that the flash module is actually accessed after wake-up, since more instructions are required than can be stored in the prefetch queue.
- Page 21 If the RTC was not running on the main oscillator, the system will not be clocked until the amplitude on the external oscillator input XTAL1 exceeds the input hysteresis. This requires typ. a few ms, depending on external crystal/oscillator circuit. With this mode, there is no oscillator watchdog function, and the system will not be clocked until the external oscillator input XTAL1 is locked.
- Page 22 BREAK_X.H1 Break on MUL/DIV followed by zero-cycle jump When a MUL or DIV instruction is immediately followed by a falsely predicted conditional zero-cycle jump (JMPR or JMPA on any condition other than cc_UC), either a 'break now' request is set at the time the MUL / DIV instruction is being executed (i.e. a break request on operand address, data, task ID, BRKIN# pin etc.
- Page 23 RSTOUT_X.H1 RSTOUT# driven by weak driver during HW Reset A weak driver (see specification in Data Sheet) has been implemented on pin RSTOUT# which is driven low while RSTIN# is asserted low. After the end of the internal reset sequence, RSTOUT# operates in default mode (strong driver/sharp edge mode, i.e.
- Page 24 When using odd values (1..15) for PLLODIV, where PLLODIV = 15 (0Fh) is selected by hardware only during clock system emergency mode or reconfiguration, the duty cycle for signal CLKOUT is on its nominal value of 50% PLLODIV Duty 33.33 42.86 44.44 45.45...
- Page 25 RTC_X.H1.2 Resetting and Disabling of the Real Time Clock Register RTC_CON is not affected by a hardware/software/watchdog reset. After power-up, it is undefined. A reset of the RTC module is achieved by setting bit SYSCON0.15/RTCRST = 1. This way, register RTC_CON is set to 8003h (RTC runs, prescaler by 8 enabled). The RTC clocking mode (synchronous, asynchronous) is determined by bit SYSCON0.14/RTCCM.
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Page 26: Documentation Update
5. Documentation Update • XC164-16 System Units - User's Manual V2.1, 2004-03: RTC_X.001 Real Time Clock operation during sleep or power down mode If the Real Time Clock shall run during sleep or power down mode, bit RTC_CON.4 (REFCLK) must be set to ‘1’...
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