Continuous Transfers - Infineon Technologies TC1728 User Manual

Master
Shift Register
Clock
Figure 18-5 SSC Half-Duplex Configuration

18.1.2.4 Continuous Transfers

When the transmit interrupt request flag is set, it indicates that the Transmit Buffer (TB)
is empty and is ready to be loaded with the next transmit data. If the TB has been
reloaded by the time the current transmission is finished, the data is immediately
transferred to the shift register and the next transmission can start without any additional
delay (according to the selected SLSO timings). On the data line, there is no gap
between the two successive frames if no delays are selected. For example, two byte
transfers would look the same as one word transfer. This feature can be used to interface
with devices that can operate with (or require more than) 16 data bits per transfer. It is
just a matter for software how long a total data frame length can be. This option can also
be used, e.g., to interface to byte-wide and word-wide devices on the same serial bus.
Note: This option can only happen in multiples of the selected basic data width, because
it would require disabling/enabling of the SSC to reprogram the basic data width
on-the-fly.
User's Manual
SSC, V1.41 2010-06
Device #1
MTSR
MRST
Clock
CLK
18-10
Synchronous Serial Interface (SSC)
Device #2
MTSR
MRST
CLK
Common
Transmit/
Device #3
Receive
Line
MTSR
MRST
CLK
TC1728
Slave
Shift Register
Clock
Slave
Shift Register
Clock
MCA06217
V1.0, 2011-12