I/O Control; Downstream Channel Output Control - Infineon Technologies TC1728 User Manual

19.1.4

I/O Control

The types of I/O control logic for the MSC module I/O lines are shown in
The downstream channel generates five output signals that control eight MSC module
outputs, split into four chip select outputs, two clock outputs, and two serial data outputs.
The upstream channel has one input signal.
Downstream
Figure 19-19 I/O Control
The MSC module I/O signals is controlled by bit fields that are located in the Output
Control Register OCR.

19.1.4.1 Downstream Channel Output Control

As shown in Figure 19-5
channel operation are indicated by three enable signals:
• ENL indicates the SRL active phase of a data frame
• ENH indicates the SRH active phase of a data frame
• ENC indicates the active phase of a command frame
The chip select output control logic of the MSC uses a signal compressing scheme
(similar to the interrupt request compressing scheme in
of the three enable signals to be directed via a 2-bit selector to one of the four chip enable
User's Manual
MSC, V1.37 2009-05
MSC Module
ENL
ENH
ENC
Channel
FCL
SO
Upstream SI
Channel
and Figure
Micro Second Channel (MSC)
Chip Select
Output
Control
Clock & Data
Output
Control
Data Input
Control
19-6, the active phases during downstream
Figure
19-27
TC1728
Figure 19-19.
EN0
EN1
EN2
EN3
FCLP
FCLN
SOP
SON
SDI[7:0]
MCA06245
19-27) that allows each
V1.0, 2011-12