Can Basics; Addressing And Bus Arbitration - Infineon Technologies TC1728 User Manual

32-bit single-chip microcontroller
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20.1

CAN Basics

CAN is an asynchronous serial bus system with one logical bus line. It has an open,
linear bus structure with equal bus participants called nodes. A CAN bus consists of two
or more nodes.
The bus logic corresponds to a "wired-AND" mechanism. Recessive bits (equivalent to
the logic 1 level) are overwritten by dominant bits (logic 0 level). As long as no bus node
is sending a dominant bit, the bus is in the recessive state. In this state, a dominant bit
from any bus node generates a dominant bus state. The maximum CAN bus speed is,
by definition, 1 Mbit/s. This speed limits the CAN bus to a length of up to 40 m. For bus
lengths longer than 40 m, the bus speed must be reduced.
The binary data of a CAN frame is coded in NRZ code (Non-Return-to-Zero). To ensure
re-synchronization of all bus nodes, bit stuffing is used. This means that during the
transmission of a message, a maximum of five consecutive bits can have the same
polarity. Whenever five consecutive bits of the same polarity have been transmitted, the
transmitter will insert one additional bit (stuff bit) of the opposite polarity into the bit
stream before transmitting further bits. The receiver also checks the number of bits with
the same polarity and removes the stuff bits from the bit stream (= destuffing).
20.1.1

Addressing and Bus Arbitration

In the CAN protocol, address information is defined in the identifier field of a message.
The identifier indicates the contents of the message and its priority. The lower the binary
value of the identifier, the higher is the priority of the message.
For bus arbitration, CSMA/CD with NDA (Carrier Sense Multiple Access/Collision
Detection with Non-Destructive Arbitration) is used. If bus node A attempts to transmit a
message across the network, it first checks that the bus is in the idle state ("Carrier
Sense") i.e. no node is currently transmitting. If this is the case (and no other node
wishes to start a transmission at the same moment), node A becomes the bus master
and sends its message. All other nodes switch to receive mode during the first
transmitted bit (Start-Of-Frame bit). After correct reception of the message
(acknowledged by each node), each bus node checks the message identifier and stores
the message, if required. Otherwise, the message is discarded.
If two or more bus nodes start their transmission at the same time ("Multiple Access"),
bus collision of the messages is avoided by bit-wise arbitration ("Collision Detection /
Non-Destructive Arbitration" together with the "Wired-AND" mechanism, dominant bits
override recessive bits). Each node that sends also reads back the bus level. When a
recessive bit is sent but a dominant one is read back, bus arbitration is lost and the
transmitting node switches to receive mode. This condition occurs for example when the
message identifier of a competing node has a lower binary value and therefore sends a
message with a higher priority. In this way, the bus node with the highest priority
message wins arbitration without losing time by having to repeat the message. Other
nodes that lost arbitration will automatically try to repeat their transmission once the bus
User's Manual
MultiCAN, V2.24
Controller Area Network Controller (MultiCAN)
20-2
TC1728
V1.0, 2011-12

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