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15.6.1
System Registers description
BMU Module Clock Control Register.
CLC
Control Clock Register
31
30
29
28
15
14
13
12
Field
Bits
DISR
0
DISS
1
0
[31:2]
Note: The BMU does not implement a fractional divider.
Note: Sleep and Suspend modes are not supported by BMU, therefore the bit fields
controlling those features are not present in the CLC register.
Note: The BMU can be disabled. When the disable state is requested all pending
transactions running on the FPI slave interface must be completed before the
disabled state is entered. The CLC Register Module Disable Bit Status
BMU_CLC.DISS indicates whether the module is currently disabled (DISS == 1).
Any attempt to write any of the BPI writable registers with the exception of the CLC
Register will generate a bus error. A read operation of BPI registers is allowed and
does not generate a bus error. As long as the BMU is disabled no logging is
possible (including the write access to the BMU_CLC register to enable again the
User's Manual
BMU, V2.6
(00
27
26
25
24
11
10
9
8
0
r
Type Description
rw
Module Disable Bit Request
Used for enable/disable control of the module
0
Module disable is not requested
B
1
Module disable is requested
B
rh
Module Disable Bit Status
Bit indicates the current status of the module
0
Module is enabled
B
1
Module is disabled
B
r
Reserved
Read as 0; write has no effect.
15-29
Bus Monitor Unit (BMU)
)
Reset Value: 0000 0000
H
23
22
21
20
r
7
6
5
rw
TC1728
19
18
17
4
3
2
1
w
rw
rw
rh
V1.0, 2011-12
H
16
0
rw
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