Infineon Technologies TC1728 User Manual page 1040

Field Bits
CMP0OS 2
CMP1EN 4
CMP1IR 5
CMP1OS 6
0 3,
[31:7]
User's Manual
STM, V1.6
Type Description
rw Compare Register CMP0 Interrupt Output Selection
This bit determines the interrupt output that is activated
on a compare match event of compare register CMP0.
0 Interrupt output STMIR0 selected
B
1 Interrupt output STMIR1 selected
B
rw Compare Register CMP1 Interrupt Enable Control
This bit enables the compare match interrupt with
compare register CMP1.
0 Interrupt on compare match with CMP1 disabled
B
1 Interrupt on compare match with CMP1 enabled
B
rh Compare Register CMP1 Interrupt Request Flag
This bit indicates whether or not a compare match
interrupt request of compare register CMP1 is pending.
CMP1IR must be cleared by software.
0 A compare match interrupt has not been detected
B
since the bit has been cleared for the last time.
1 A compare match interrupt has been detected.
B
CMPIR1 must be cleared by software and can be set by
software, too (see CMPISRR register). After a STM
reset, CMP1IR is immediately set as a result of a
compare match event with the reset values of the STM
and the compare register CMP1.
rw Compare Register CMP1 Interrupt Output Selection
This bit determines the interrupt output that is activated
on a compare match event of compare register CMP1.
0 Interrupt output STMIR0 selected
B
1 Interrupt output STMIR1 selected
B
r Reserved
Read as 0; should be written with 0.
14-18
TC1728
System Timer (STM)
V1.0, 2011-12