Bmu Control/Status Registers - Infineon Technologies TC1728 User Manual

15.6.2

BMU Control/Status Registers

CTL
Transaction Filtering Control
31
Field Bits
MODE 0
TMF 1
0 [31:2]
CTL defines the access mode to the internal SRAM and enables to control additional
logging mechanisms based on the initiator of the transaction. The operation mode is
statically defined for the whole run-time, changes of operating mode are to be avoided.
In the event the BMU is configured in FIFO mode (CTL.MODE = 1) then the CTL
register should be polled to confirm the FIFO mode is set before any write
transaction on the FPI bus is logged.
However when the BMU is configured in FIFO mode, it may be necessary to switch to
SRAM mode if run time diagnostics of the ECC logic is required. It must be ensured at
system level that during the time the diagnostics will be performed, the safety application
User's Manual
BMU, V2.6
(20
0
r
Type Description
rw Access Mode
0 The BTF is accessed in linear mode as a standard
B
memory mapped SRAM
1 The BTF is used in FIFO Mode enabling to log the
B
write transaction to the regions selected in
and PSET1
rw Transaction Master Filtering
In FIFO mode, this field enables an additional logging
mechanism controlled by the master identifier of a FPI
write transaction.
0 Logging controlled by the transaction master
B
identifier disabled.
1 Logging controlled by the transaction master
B
identifier Enabled.
r reserved bit fields. A write has no effect. Returns 0s on
read.
15-32
Bus Monitor Unit (BMU)
) Reset Value: 0000 0000
H
registers.
TC1728
H
0
M
T
O
M
D
F
E
rw rw
PSET0
V1.0, 2011-12