Samsung S5PC110 Manual page 1001

S5PC110_UM 7 SD/MMC CONTROLLER
7.6 DMA TRANSACTION
DMA allows a peripheral to read and write memory without intervention from the CPU. DMA executes one SD
command transaction. Host Controllers that support DMA supports both single block and multiple block transfers.
The System Address register points to the first data address, and data is then accessed sequentially from that
address. Host Controller registers remains accessible for issuing non-DAT line commands during a DMA transfer.
The result of a DMA transfer is same regardless of the system bus transaction method. DMA does not support
infinite transfers.
DMA transfers are stopped and restarted using control bits in the Block Gap Control register. If the Stop At Block
Gap Request is set, DMA transfers is suspended. If the Continue Request is set or a Resume Command is
issued, DMA continues to execute transfers. Refer to the Block Gap Control register for details. If SD Bus errors
occur, SD Bus transfers and DMA transfers are stopped. Setting the Software Reset for DAT Line in the
Software Reset register aborts DMA transfers.
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