Motorola MPC823e Reference Manual page 1118

LBRK—Load/Store Breakpoint Interrupt
This bit is set as a result of the assertion of an load/store breakpoint. The core enters debug
mode if enabled and the LBRKE bit in the DER is set.
IBRK—Instruction Breakpoint Interrupt
This bit is set as a result of the assertion of an instruction breakpoint. The core enters debug
mode if enabled and the IBRKE bit in the DER is set.
EBRK—External Breakpoint Interrupt
This bit is set as a result of the assertion of an external breakpoint. The core enters debug
mode if enabled and the EBRKE bit in the DER is set.
DPI—Development Port Interrupt
This bit is set by the development port as a result of a debug station nonmaskable request
or when entering debug mode immediately out of reset. The core enters debug mode if
enabled and the DPIE bit in the DER is set.
20.6.3.2 DEBUG ENABLE REGISTER. The debug enable register (DER) allows the
enabling of events that cause the processor to enter debug mode.
DER
BIT 0 1 2
CHSTP
FIELD
RES RSTE
E
RESET
0 0 1
R/W
R/W R/W R/W
SPR
BIT 16 17 18
ITLBMS DTLBM
FIELD
RES SEIE
E
RESET
0 0 0
R/W
R/W R/W R/W
SPR
Bits 0, 4, and 5—Reserved
These bits are reserved and must be set to 0.
RSTE—Reset Interrupt Enable
0 = Debug mode entry is disabled (reset value).
1 = Debug mode entry is enabled.
MOTOROLA
3 4 5 6 7
MCIE RESERVED EXTIE ALIE
0 0 0 0
R/W R/W R/W R/W
149
19 20 21 22 23
DTLBER
ITLBERE
SE E
0 0 0
R/W R/W R/W
149
MPC823e REFERENCE MANUAL
Development Capabilities and Interface
8 9 10 11 12
FPUVI
PRIE DECIE RESERVED SYSIE
E
0 0 0 0
R/W R/W R/W R/W
24 25 26 27 28
RESERVED LBRKE IBRKE
0 1
R/W R/W
13 14 15
TRE RES
0 1 0
R/W R/W R/W
29 30 31
EBRKE DPIE
1 1 1
R/W R/W R/W
20-57