Hash Registers; Hash Control Register (Hash_Cr) - ST STM32F207 Series Reference Manual

RM0033
21.4

HASH registers

The HASH core is associated with several control and status registers and five message
digest registers.
All these registers are accessible through word accesses only, else an AHB error is
generated.
21.4.1

HASH control register (HASH_CR)

Address offset: 0x00
Reset value: 0x0000 0000
31 30 29
15 14 13
DINNE
Reserved
Bits 31:17 Reserved, forced by hardware to 0.
Bits 15:13 Reserved, forced by hardware to 0.
28 27 26 25
12 11 10 9
NBW
r r r r
Bit 16 LKEY: Long key selection
This bit selects between short key (≤ 64 bytes) or long key (> 64 bytes) in HMAC
mode
0: Short key (≤ 64 bytes)
1: Long key (> 64 bytes)
Note: This selection is only taken into account when the INIT bit is set and MODE
= 1. Changing this bit during a computation has no effect.
Bit 12 DINNE: DIN not empty
This bit is set when the HASH_DIN register holds valid data (that is after being
written at least once). It is cleared when either the INIT bit (initialization) or the
DCAL bit (completion of the previous message processing) is written to 1.
0: No data are present in the data input buffer
1: The input buffer contains at least one word of data
24 23 22
Reserved
8 7 6
ALGO[0] MODE
r rw rw
RM0033 Rev 9
Hash processor (HASH)
21 20 19 18
5 4 3 2
DATATYPE DMAE INIT
rw rw rw w
17 16
LKEY
rw
1 0
Reserved
559/1381
569