Otg_Hs Interrupts - ST STM32F207 Series Reference Manual

Advanced arm-based 32-bit mcus

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Bandwidth Isochronous OUT endpoint, then the space must be at least two times the

maximum packet size for that channel.

More space allocated in the Transmit nonperiodic FIFO results in better performance on the

When operating in DMA mode, the DMA address register for each host channel (HCDMAn)

is stored in the SPRAM (FIFO). One location for each channel must be reserved for this.

OTG_HS interrupts

When the OTG_HS controller is operating in one mode, either peripheral or host, the

application must not access registers from the other mode. If an illegal access occurs, a

mode mismatch interrupt is generated and reflected in the Core interrupt register (MMIS bit

in the OTG_HS_GINTSTS register). When the core switches from one mode to the other,

the registers in the new mode of operation must be reprogrammed as they would be after a

power-on reset.

shows the interrupt hierarchy.

RM0033 Rev 9

USB on-the-go high-speed (OTG_HS)

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