Dcmi Interrupts; Dcmi Register Description; Dcmi Control Register 1 (Dcmi_Cr); Table 52. Data Storage In Ycbcr Progressive Video Format - ST STM32F207 Series Reference Manual

Digital camera interface (DCMI)
Byte address
12.7

DCMI interrupts

Five interrupts are generated. All interrupts are maskable by software. The global interrupt
(IT_DCMI) is the OR of all the individual interrupts.
Interrupt name
IT_LINE
IT_FRAME
IT_OVR
IT_VSYNC
IT_ERR
IT_DCMI
12.8

DCMI register description

All DCMI registers have to be accessed as 32-bit words, otherwise a bus error occurs.
12.8.1

DCMI control register 1 (DCMI_CR)

Address offset: 0x00
Reset value: 0x0000 0x0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit 31:15 Reserved, must be kept at reset value.
Bit 13: 12 Reserved, must be kept at reset value.
290/1381

Table 52. Data storage in YCbCr progressive video format

31:24
0 Y n + 1
4 Y n + 3
Indicates the end of line
Indicates the end of frame capture
indicates the overrun of data reception
Indicates the synchronization frame
Indicates the detection of an error in the embedded synchronization frame
detection
Logic OR of the previous interrupts
Reserved
Bit 14 ENABLE: DCMI enable
0: DCMI disabled
1: DCMI enabled
Note: The DCMI configuration registers should be programmed correctly before
enabling this Bit
23:16
Cr n
Cr n + 2
Table 53

Table 53. DCMI interrupts

Interrupt event
rw rw rw rw rw rw rw rw rw rw rw rw rw
RM0033 Rev 9
15:8
Y n
Y n + 2
gives the list of all interrupts.
9 8 7 6 5
EDM FCRC
RM0033
7:0
Cb n
Cb n + 2
4 3 2 1 0