Otg_Hs Control And Status Registers; Csr Memory Map - ST STM32F207 Series Reference Manual

RM0033
30.12

OTG_HS control and status registers

By reading from and writing to the control and status registers (CSRs) through the AHB
slave interface, the application controls the OTG_HS controller. These registers are 32 bits
wide, and the addresses are 32-bit block aligned. The OTG_HS registers must be accessed
by words (32 bits). CSRs are classified as follows:
• Core global registers
•
Host-mode registers
• Host global registers
•
Host port CSRs
• Host channel-specific registers
•
Device-mode registers
• Device global registers
•
Device endpoint-specific registers
• Power and clock-gating registers
•
Data FIFO (DFIFO) access registers
Only the Core global, Power and clock-gating, Data FIFO access, and host port control and
status registers can be accessed in both host and peripheral modes. When the OTG_HS
controller is operating in one mode, either peripheral or host, the application must not
access registers from the other mode. If an illegal access occurs, a mode mismatch
interrupt is generated and reflected in the Core interrupt register (MMIS bit in the
OTG_HS_GINTSTS register). When the core switches from one mode to the other, the
registers in the new mode of operation must be reprogrammed as they would be after a
power-on reset.
30.12.1

CSR memory map

The host and peripheral mode registers occupy different addresses. All registers are
implemented in the AHB clock domain.
USB on-the-go high-speed (OTG_HS)
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