Ethernet (ETH): media access control (MAC) with DMA controller
MII/RMII transmit timing diagrams
MII_TX_CLK
MII_TX_EN
MII_TXD[3:0]
MII_COL
860/1381
Figure 325. Transmission bit order
LSB
MII_TXD[3:0]
MSB
Nibble stream
Figure 326. Transmission with no collision
PR
MII_CS
Low
LSB
MSB
D0
D1
D0
D1
D2
D3
EA
MB
LE
RM0033 Rev 9
Bibit stream
ai15632
RM0033
ai15631
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