Gpio Alternate Function Low Register (Gpiox_Afrl) (X = A - ST STM32F207 Series Reference Manual

RM0033
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 LCKK[16]: Lock key
Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.
Bits 15:0 LCKy: Port x lock bit y (y= 0..15)
6.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A..I)
Address offset: 0x20
Reset value: 0x0000 0000
31 30 29
AFRL7[3:0]
rw rw rw
15 14 13
AFRL3[3:0]
rw rw rw
Bits 31:0 AFRLy: Alternate function selection for port x bit y (y = 0..7)
This bit can be read any time. It can only be modified using the lock key write sequence.
0: Port configuration lock key not active
1: Port configuration lock key active. The GPIOx_LCKR register is locked until an MCU reset
or a peripheral reset occurs.
LOCK key write sequence:
WR LCKR[16] = '1' + LCKR[15:0]
WR LCKR[16] = '0' + LCKR[15:0]
WR LCKR[16] = '1' + LCKR[15:0]
RD LCKR
RD LCKR[16] = '1' (this read operation is optional but it confirms that the lock is active)
Any error in the lock sequence aborts the lock.
After the first lock sequence on any bit of the port, any read access on the LCKK bit
returns '1' until the next CPU reset.
These bits are read/write but can only be written when the LCKK bit is '0.
0: Port configuration not locked
1: Port configuration locked
28 27 26 25
AFRL6[3:0]
rw rw rw rw
12 11 10 9
AFRL2[3:0]
rw rw rw rw
These bits are written by software to configure alternate function I/Os
AFRLy selection:
0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7
24 23 22
AFRL5[3:0]
rw rw rw
8 7 6
AFRL1[3:0]
rw rw rw
1000: AF8
1001: AF9
1010: AF10
1011: AF11
1100: AF12
1101: AF13
1110: AF14
1111: AF15
RM0033 Rev 9
General-purpose I/Os (GPIO)
21 20 19 18
AFRL4[3:0]
rw rw rw rw
5 4 3 2
AFRL0[3:0]
rw rw rw rw
17 16
rw rw
1 0
rw rw
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