Table 100. Audio Frequency Precision (For Pllm Vco = 1 Mhz Or 2 Mhz); Figure 283. I - ST STM32F207 Series Reference Manual

RM0033
I²SxCLK
1. Where x could be 2 or 3.
Figure 282
performance, the I2SxCLK clock source can be either the PLLI2S output (through R division
factor) or an external clock (mapped to I2S_CKIN pin).
The audio sampling frequency can be 96 kHz, 48 kHz, 44.1 kHz, 32 kHz, 22.05 kHz,
16 kHz, 11.025 kHz or 8 kHz (or any other value within this range). In order to reach the
desired frequency, the linear divider needs to be programmed according to the formulas
below:
When the master clock is generated (MCKOE in the SPI_I2SPR register is set):
F = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD)*8)] when the channel frame is 16-bit wide
S
F = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD)*4)] when the channel frame is 32-bit wide
S
When the master clock is disabled (MCKOE bit cleared):
F = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD))] when the channel frame is 16-bit wide
S
F = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD))] when the channel frame is 32-bit wide
S
Table 100
Note: Other configurations are possible that allow optimum clock precision.

Table 100. Audio frequency precision (for PLLM VCO = 1 MHz or 2 MHz)

Master Target f
S
clock (Hz)

Figure 283. I

8-bit linear divider
+ reshaping stage
I²SDIV[7:0]
MCKOE ODD
presents the communication clock architecture. To achieve high-quality audio
provides example precision values for different clock configurations.
Data
PLLI2SN
format
2
S clock generator architecture
Divider by 4
PLLI2SR I2SDIV I2SODD
RM0033 Rev 9
Serial peripheral interface (SPI)
0
0
Div2
1
1
MCKOE
(1)
Real f (Hz)
S
MCK
CK
MS30109V1
Error
717/1381
734