Message Padding - ST STM32F207 Series Reference Manual

RM0033
21.3.4

Message padding

Message padding consists in appending a "1" followed by m "0"s followed by a 64-bit integer
to the end of the original message to produce a padded message block of length 512. The
"1" is added to the last word written into the HASH_DIN register at the bit position defined by
the NBLW bitfield, and the remaining upper bits are cleared ("0"s).
Example: let us assume that the original message is the ASCII binary-coded form of "abc",
of length L = 24:
byte 0
01100001 01100010 01100011 UUUUUUUU
<-- 1st word written to HASH_DIN -->
NBLW has to be loaded with the value 24: a "1" is appended at bit location 24 in the bit string
(starting counting from left to right in the above bit string), which corresponds to bit 31 in the
HASH_DIN register (little-endian convention):
01100001 01100010 01100011 1UUUUUUU
Since L = 24, the number of bits in the above bit string is 25, and 423 "0"s are appended,
making now 448. This gives (in hexadecimal, big-endian format):
61626380 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000
The L value, in two-word representation (that is 00000000 00000018) is appended. Hence
the final padded message in hexadecimal:
61626380 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000028
If the HASH is programmed to use the little-endian byte input format, the above message
has to be entered by doing the following steps:
1. 0xUU636261 is written into the HASH_DIN register (where 'U' means don't care)
2. 0x18 is written into the HASH_STR register (the number of valid bits in the last word
written into the HASH_DIN register is 24, as the original message length is 24 bits)
3. 0x10 is written into the HASH_STR register to start the message padding and digest
computation. When NBLW ≠ 0x00, the message padding puts a "1" into the HASH_DIN
register at the bit position defined by the NBLW value, and inserts "0"s at bit locations
[31:(NBLW+1)]. When NBLW == 0x00, the message padding inserts one new word with
value 0x0000 0001. Then an all zero word (0x0000 0000) is added and the message
length in a two-word representation, to get a block of 16 x 32-bit words.
4. The HASH computing is performed, and the message digest is then available in the
HASH_Hx registers (x = 0...4) for the SHA-1 algorithm. For example:
H0 = 0xA9993E36
H1 = 0x4706816A
H2 = 0xBA3E2571
H3 = 0x7850C26C
H4 = 0x9CD0D89D
byte 1 byte 2
RM0033 Rev 9
byte 3
Hash processor (HASH)
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