Spi Interrupts; Table 99. Spi Interrupt Requests; Figure 263. Ti Mode Frame Format Error Detection - ST STM32F207 Series Reference Manual

RM0033
CRC error
This flag is used to verify the validity of the value received when the CRCEN bit in the
SPI_CR1 register is set. The CRCERR flag in the SPI_SR register is set if the value
received in the shift register does not match the receiver SPI_RXCRCR value.
TI mode frame format error
A TI mode frame format error is detected when an NSS pulse occurs during an ongoing
communication when the SPI is acting in slave mode and configured to conform to the TI
mode protocol. When this error occurs, the TIFRFE flag is set in the SPI_SR register. The
SPI is not disabled when an error occurs, the NSS pulse is ignored, and the SPI waits for
the next NSS pulse before starting a new transfer. The data may be corrupted since the
error detection may result in the lost of two data bytes.
The TIFRFE flag is cleared when SPI_SR register is read. If the bit ERRIE is set, an
interrupt is generated on the NSS error detection. In this case, the SPI should be disabled
because data consistency is no more guaranteed and communications should be reinitiated
by the master when the slave SPI is re-enabled.
NSS
output
trigger
SCK
output
MOSI
DONTCARE
input
MISO
1 or 0
output
TIFRFE
25.3.11

SPI interrupts

Transmit buffer empty flag
Receive buffer not empty flag
Master Mode fault event
Overrun error
CRC error flag
TI frame format error

Figure 263. TI mode frame format error detection

sampling trigger sampling trigger sampling
MSBIN
MSBOUT

Table 99. SPI interrupt requests

Interrupt event
RM0033 Rev 9
trigger sampling trigger sampling trigger
LSBIN DONTCARE MSBIN
LSBOUT
Event flag
TXE
RXNE
MODF
OVR
CRCERR
TIFRFE
Serial peripheral interface (SPI)
sampling trigger sampling
LSBIN
MSBOUT LSBOUT
Enable Control bit
TXEIE
RXNEIE
ERRIE
ERRIE
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