Revision History; Table 11. Document Revision History - ST STM32F205 Programming Manual

PM0059
3

Revision history

Date
24-Jun-2010
09-Dec-2010
30-Mar-2011

Table 11. Document revision history

Revision
Updated memory organization in
replace user-specific block by OTP area.
Updated addresses in
Definition of BOR_LEV[3:2] bits updated in
the option bytes
(FLASH_OPTCR). Modified FLASH_OPTCR reset value in
1
Section 2.8.6: Flash option control register (FLASH_OPTCR)
Table 10: Flash register map and reset
OPTLOCK
definition.
Updated definition of ERRIE bit in
register (FLASH_CR).
Updated size of OTP area, and option byte base address and size
in
Table 2: Flash module
Changed 1.62 to 2.1 V range to 1.8 to 2.1 V, added Note 1 as well
as
wait states 4 to 7 in
CPU clock (HCLK)
Updated
Table 4: Program/erase parallelism.
Updated BOR_LEVEL description in
option bytes.
Renamed FLASH_FOCR, FLASH_OPTCR in
Programming user option
2
Updated Level 1 and Level 2 descriptions in
protection (RDP).
Updated LATENCY bits in
register (FLASH_ACR)
Changed access type to bits 0 to 7 to rc-1, and OPERR
description
in
Section 2.8.4: Flash status register
Changed access type to bits 16 and 31 to rs in
Flash control register
Changed access type to bits 0 and 1 to rs, and added note related
to
bit 7 to 5 in
(FLASH_OPTCR).
Updated OTP area in
Updated
Section 2.5: Erase and program operations
the
3
fact that read operations cannot be performed during write/erase
operations.
DocID15687 Rev 5
Changes
Section 2.3: Flash
Table 6: Option byte
and
Section 2.8.6: Flash option control register
Section 2.8.5: Flash control
organization.
TTable 3: Number of wait states according to
frequency.
bytes.
Section 2.8.1: Flash access control
to support up to 7 wait states.
(FLASH_CR).
Section 2.8.6: Flash option control register
Section 2.3: Flash
Revision history
memory, and
organization.
Table 7: Description of
values. Updated
Table 7: Description of the
Section 2.6.2:
Section 2.6.3: Read
(FLASH_SR).
Section 2.8.5:
memory.
to mention
and
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