Rcc Ahb1 Peripheral Clock Register (Rcc_Ahb1Enr) - ST STM32F205 series Reference Manual

Reset and clock control (RCC)
5.3.10

RCC AHB1 peripheral clock register (RCC_AHB1ENR)

Address offset: 0x30
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29 28
ETHMA
OTGHS OTGHS
CPTPE
Reser-
ULPIEN EN
ved
rw rw rw
15 14 13 12
CRCEN
Reserved
rw
Bits 31 Reserved, always read as 0.
Bit 30 OTGHSULPIEN: USB OTG HSULPI clock enable
Set and cleared by software.
0: USB OTG HS ULPI clock disabled
1: USB OTG HS ULPI clock enabled
Bit 29 OTGHSEN: USB OTG HS clock enable
Set and cleared by software.
0: USB OTG HS clock disabled
1: USB OTG HS clock enabled
Bit 28 ETHMACPTPEN: Ethernet PTP clock enable
Set and cleared by software.
0: Ethernet PTP clock disabled
1: Ethernet PTP clock enabled
Bit 27 ETHMACRXEN: Ethernet Reception clock enable
Set and cleared by software.
0: Ethernet Reception clock disabled
1: Ethernet Reception clock enabled
Bit 26 ETHMACTXEN: Ethernet Transmission clock enable
Set and cleared by software.
0: Ethernet Transmission clock disabled
1: Ethernet Transmission clock enabled
Bit 25 ETHMACEN: Ethernet MAC clock enable
Set and cleared by software.
0: Ethernet MAC clock disabled
1: Ethernet MAC clock enabled
Bits 24:23 Reserved, always read as 0.
Bit 22 DMA2EN: DMA2 clock enable
Set and cleared by software.
0: DMA2 clock disabled
1: DMA2 clock enabled
112/1378
27 26 25
ETHMA ETHMA ETHMA
CRXEN CTXEN CEN
N
rw rw rw
11 10 9
Reserved
24 23 22
DMA2EN DMA1EN
Reserved
rw
8 7 6
GPIOIE GPIOH GPIOGE GPIOFE
N EN N
rw rw rw
RM0033 Rev 8
21 20 19 18
BKPSR
AMEN
Reserved
rw rw
5 4 3 2
GPIOE GPIOD GPIOC
N EN EN EN
rw rw rw rw
RM0033
17 16
Reserved
1 0
GPIOB GPIOA
EN EN
rw rw