Rcc Apb2 Peripheral Clock Enabled In Low Power Mode Register (Rcc_Apb2Lpenr) - ST STM32F207 Series Reference Manual

RM0033
5.3.19 RCC APB2 peripheral clock enabled in low power mode register
(RCC_APB2LPENR)
Address offset: 0x64
Reset value: 0x0007 5F33
Access: no wait state, word, half-word and byte access.
31 30 29 28
15 14 13 12
SYSC
SPI1
FG
Reser- Reser-
LPEN
LPEN
ved ved
rw rw
Bits 31:19
Bit 18 TIM11LPEN: TIM11 clock enable during Sleep mode
Bit 17 TIM10LPEN: TIM10 clock enable during Sleep mode
Bit 16 TIM9LPEN: TIM9 clock enable during sleep mode
Bit 15
Bit 14 SYSCFGLPEN: System configuration controller clock enable during Sleep mode
Bits 13
Bit 12 SPI1LPEN: SPI 1 clock enable during Sleep mode
Bit 11 SDIOLPEN: SDIO clock enable during Sleep mode
27 26 25
Reserved
11 10 9
SDIO ADC3 ADC2
LPEN LPEN LPEN
rw rw rw
Reserved, always read as 0.
Set and cleared by software.
0: TIM11 clock disabled during Sleep mode
1: TIM11 clock enabled during Sleep mode
Set and cleared by software.
0: TIM10 clock disabled during Sleep mode
1: TIM10 clock enabled during Sleep mode
Set and cleared by software.
0: TIM9 clock disabled during Sleep mode
1: TIM9 clock enabled during Sleep mode
Reserved, always read as 0.
Set and cleared by software.
0: System configuration controller clock disabled during Sleep mode
1: System configuration controller clock enabled during Sleep mode
Reserved, always read as 0.
Set and cleared by software.
0: SPI 1 clock disabled during Sleep mode
1: SPI 1 clock enabled during Sleep mode
Set and cleared by software.
0: SDIO module clock disabled during Sleep mode
1: SDIO module clock enabled during Sleep mode
24 23 22 21
8 7 6
USART
ADC1
LPEN
Reserved
LPEN
rw rw
RM0033 Rev 9
Reset and clock control (RCC)
20 19 18
TIM11
LPEN
rw
5 4 3 2
USART
6 1
Reserved
LPEN
rw
17 16
TIM10 TIM9
LPEN LPEN
rw rw
1 0
TIM8 TIM1
LPEN LPEN
rw rw
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