Rcc Plli2S Configuration Register (Rcc_Plli2Scfgr) - ST STM32F207 Series Reference Manual

RM0033
5.3.23

RCC PLLI2S configuration register (RCC_PLLI2SCFGR)

Address offset: 0x84
Reset value: 0x2000 3000
Access: no wait state, word, half-word and byte access.
This register is used to configure the PLLI2S clock outputs according to the formulas:
•
f
(VCO clock)
•
f
(PLL I2S clock output)
31 30 29
PLLI2S PLLI2S
Reserv
R2 R1
ed
rw rw
15 14 13
PLLI2SN PLLI2SN
Reserv
8 7
ed
rw rw
Bit 31 Reserved, always read as 0.
Bits 30:28 PLLI2SR: PLLI2S division factor for I2S clocks
Set and cleared by software to control the I2S clock frequency. These bits should be written
only if the PLLI2S is disabled. The factor must be chosen in accordance with the prescaler
values inside the I2S peripherals, to reach 0.3% error when using standard crystals and 0%
error with audio crystals. For more information about I2S clock frequency and precision, refer
to
Caution: The I2Ss requires a frequency lower than or equal to 192 MHz to work correctly.
= f
(PLLI2S clock input)
= f
(VCO clock)
28 27 26
PLLI2S
R0
rw
12 11 10
PLLI2SN PLLI2SN PLLI2SN
6 5 4
rw rw rw
Section 25.4.3: Clock generator
I2S clock frequency = VCO frequency / PLLR with 2 ≤ PLLR ≤ 7
000: PLLR = 0, wrong configuration
001: PLLR = 1, wrong configuration
010: PLLR = 2
...
111: PLLR = 7
× (PLLI2SN / PLLM)
/ PLLI2SR
25 24 23
Reserved
9 8 7
PLLI2SN PLLI2SN PLLI2SN
3 2 1
rw rw rw
in the I2S chapter.
RM0033 Rev 9
Reset and clock control (RCC)
22 21 20 19
6 5 4 3
PLLI2SN
0
Reserved
rw
18 17 16
2 1 0
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