Power Management: Pmt; Figure 334. Wakeup Frame Filter Register - ST STM32F207 Series Reference Manual

RM0033
Received frames are considered "good" if none of the following errors exists:
+ CRC error
+ Runt Frame (shorter than 64 bytes)
+ Alignment error (in 10/ 100 Mbit/s only)
+ Length error (non-Type frames only)
+ Out of Range (non-Type frames only, longer than maximum size)
+ MII_RXER Input error
The maximum frame size depends on the frame type, as follows:
+ Untagged frame maxsize = 1518
+ VLAN Frame maxsize = 1522
28.5.8

Power management: PMT

This section describes the power management (PMT) mechanisms supported by the MAC.
PMT supports the reception of network (remote) wakeup frames and Magic Packet frames.
PMT generates interrupts for wakeup frames and Magic Packets received by the MAC. The
PMT block is enabled with remote wakeup frame enable and Magic Packet enable. These
enable bits (WFE and MPE) are in the ETH_MACPMTCSR register and are programmed by
the application. When the power down mode is enabled in the PMT, then all received frames
are dropped by the MAC and they are not forwarded to the application. The MAC comes out
of the power down mode only when either a Magic Packet or a Remote wakeup frame is
received and the corresponding detection is enabled.
Remote wakeup frame filter register
There are eight wakeup frame filter registers. To write on each of them, load the wakeup
frame filter register value by value. The wanted values of the wakeup frame filter are loaded
by sequentially loading eight times the wakeup frame filter register. The read operation is
identical to the write operation. To read the eight values, you have to read eight times the
wakeup frame filter register to reach the last register. Each read/write points the wakeup
frame filter register to the next filter register.
Wakeup frame filter reg0
Wakeup frame filter reg1
Wakeup frame filter reg2
Wakeup frame filter reg3
Wakeup frame filter reg4
Wakeup frame filter reg5
Wakeup frame filter reg6
Wakeup frame filter reg7
Ethernet (ETH): media access control (MAC) with DMA controller

Figure 334. Wakeup frame filter register

Filter 3
RSVD RSVD
Command
Filter 3 Offset Filter 2 Offset
Filter 1 CRC - 16
Filter 3 CRC - 16
RM0033 Rev 9
Filter 0 Byte Mask
Filter 1 Byte Mask
Filter 2 Byte Mask
Filter 3 Byte Mask
Filter 2 Filter 1
RSVD
Command Command
Filter 1 Offset
Filter 0 CRC - 16
Filter 2 CRC - 16
Filter 0
RSVD
Command
Filter 0 Offset
ai15647
871/1381
956