Figure 234. Usart Example Of Synchronous Transmission; Figure 235. Usart Data Clock Timing Diagram (M=0) - ST STM32F207 Series Reference Manual

Universal synchronous asynchronous receiver transmitter (USART)
has been written). This means that it is not possible to receive a synchronous data without
transmitting data.
The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. These
bits should not be changed while the transmitter or the receiver is enabled.
It is advised that TE and RE are set in the same instruction in order to minimize the setup
and the hold time of the receiver.
The USART supports master mode only: it cannot receive or send data related to an input
clock (CK is always an output).
Idle or preceding
transmission
Clock (CPOL=0, CPHA=0
Clock (CPOL=0, CPHA=1
Clock (CPOL=1, CPHA=0
Clock (CPOL=1, CPHA=1
Data on TX
(from master)
Data on RX
(from slave)
Capture strobe
658/1381

Figure 234. USART example of synchronous transmission

USART

Figure 235. USART data clock timing diagram (M=0)

Start
0 1
LSB
Start
0 1
LSB
RM0033 Rev 9
RX Data out
TX Data in
Synchronous device
(e.g. slave SPI)
Clock
CK
M=0 (8 data bits)
2 3 4 5
2 3 4 5
*LBCL bit controls last data pulse
RM0033
MSv31158V2
Idle or next
Stop
transmission
*
*
*
*
6 7
MSB Stop
6 7
MSB
*
MSv31159V1