Table 201. 16-Bit Nand Flash; Table 202. 16-Bit Pc Card - ST STM32F207 Series Reference Manual

RM0033
16-bit NAND Flash
FSMC signal name
A[17]
A[16]
D[15:0]
NCE[x]
NOE(= NRE)
NWE
NWAIT/INT[3:2]
There is no theoretical capacity limitation as the FSMC can manage as many address
cycles as needed.
16-bit PC Card
FSMC signal name
A[10:0]
NIORD
NIOWR
NREG
D[15:0]
NCE4_1
NCE4_2
NOE
NWE
NWAIT
INTR

Table 201. 16-bit NAND Flash

I/O
O
O
I/O
O
O
O
I
I/O
O Address bus
O Output enable for I/O space
O Write enable for I/O space
O Register signal indicating if access is in Common or Attribute space
I/O Bidirectional databus
O Chip select 1
O Chip select 2 (indicates if access is 16-bit or 8-bit)
O Output enable in Common and in Attribute space
O Write enable in Common and in Attribute space
PC Card wait input signal to the FSMC (memory signal name
I
IORDY)
PC Card interrupt to the FSMC (only for PC Cards that can generate
I
an interrupt)
PC Card presence detection. Active high. If an access is performed
CD I to the PC Card banks while CD is low, an AHB error is generated.
Refer to
Flexible static memory controller (FSMC)
NAND Flash address latch enable (ALE) signal
NAND Flash command latch enable (CLE) signal
16-bit multiplexed, bidirectional address/data bus
Chip select, x = 2, 3
Output enable (memory signal name: read enable, NRE)
Write enable
NAND Flash ready/busy input signal to the FSMC

Table 202. 16-bit PC Card

Section 31.3: AHB interface
RM0033 Rev 9
Function
Function
1303/1381
1318