Table 163. Device-Mode Control And Status Registers - ST STM32F207 Series Reference Manual

USB on-the-go high-speed (OTG_HS)
Table 162. Host-mode control and status registers (CSRs) (continued)
Acronym
OTG_HS_HCCHARx
OTG_HS_HCSPLTx
OTG_HS_HCINTx
OTG_HS_HCINTMSKx 0x50C
OTG_HS_HCTSIZx
OTG_HS_HCDMAx
Device-mode CSR map
These registers must be programmed every time the core changes to peripheral mode.
Acronym
OTG_HS_DCFG
OTG_HS_DCTL
OTG_HS_DSTS
OTG_HS_DIEPMSK
OTG_HS_DOEPMSK
OTG_HS_DAINT
OTG_HS_DAINTMSK
OTG_HS_DVBUSDIS
OTG_HS_DVBUSPULSE
OTG_HS_DTHRCTL
1122/1381
Offset
address
0x500
0x520
OTG_HS host channel-x characteristics register (OTG_HS_HCCHARx)
(x = 0..11, where x = Channel_number) on page 1154
...
0x660
OTG_HS host channel-x split control register (OTG_HS_HCSPLTx)
0x504
(x = 0..11, where x = Channel_number) on page 1156
OTG_HS host channel-x interrupt register (OTG_HS_HCINTx) (x = 0..11,
0x508
where x = Channel_number) on page 1157
OTG_HS host channel-x interrupt mask register (OTG_HS_HCINTMSKx)
(x = 0..11, where x = Channel_number) on page 1158
OTG_HS host channel-x transfer size register (OTG_HS_HCTSIZx)
0x510
(x = 0..11, where x = Channel_number) on page 1159
OTG_HS host channel-x DMA address register (OTG_HS_HCDMAx)
0x514
(x = 0..11, where x = Channel_number) on page 1160

Table 163. Device-mode control and status registers

Offset
address
OTG_HS device configuration register (OTG_HS_DCFG) on
0x800
page 1160
0x804 OTG_HS device control register (OTG_HS_DCTL) on page 1162
0x808 OTG_HS device status register (OTG_HS_DSTS) on page 1164
OTG_HS device IN endpoint common interrupt mask register
0x810
(OTG_HS_DIEPMSK) on page 1165
OTG_HS device OUT endpoint common interrupt mask register
0x814
(OTG_HS_DOEPMSK) on page 1166
OTG_HS device all endpoints interrupt register (OTG_HS_DAINT)
0x818
on page 1167
OTG_HS all endpoints interrupt mask register
0x81C
(OTG_HS_DAINTMSK) on page 1168
OTG_HS device V
0x828
(OTG_HS_DVBUSDIS) on page 1168
OTG_HS device V
0x82C
(OTG_HS_DVBUSPULSE) on page 1169
OTG_HS Device threshold control register (OTG_HS_DTHRCTL)
0x830
on page 1170
Register name
discharge time register
BUS
pulsing time register
BUS
RM0033 Rev 9
Register name
RM0033