C Clock Control Register (I2C_Ccr) - ST STM32F207 Series Reference Manual

RM0033
2
23.6.8 I

C Clock control register (I2C_CCR)

Address offset: 0x1C
Reset value: 0x0000
Note: f must be at least 2 MHz to achieve Sm mode I²C frequencies. It must be at least 4
PCLK1
MHz to achieve Fm mode I²C frequencies. It must be a multiple of 10MHz to reach the
400 kHz maximum I²C Fm mode clock.
The CCR register must be configured only when the I2C is disabled (PE = 0).
15 14 13 12
F/S DUTY
Reserved
rw rw
Bit 15 F/S: I2C master mode selection
Bit 14 DUTY: Fm mode duty cycle
Bits 13:12 Reserved, must be kept at reset value
Bits 11:0 CCR[11:0]: Clock control register in Fm/Sm mode (Master mode)
Note: The minimum allowed value is 0x04, except in FAST DUTY mode where the minimum
11 10 9
rw rw rw
0: Sm mode I2C
1: Fm mode I2C
0: Fm mode t /t = 2
low high
1: Fm mode t /t = 16/9 (see CCR)
low high
Controls the SCL clock in master mode.
Sm mode or SMBus:
T = CCR * T
high PCLK1
T = CCR * T
low PCLK1
Fm mode:
If DUTY = 0:
T = CCR * T
high PCLK1
T = 2 * CCR * T
low PCLK1
If DUTY = 1:
T = 9 * CCR * T
high PCLK1
T = 16 * CCR * T
low PCLK1
For instance: in Sm mode, to generate a 100 kHz SCL frequency:
If FREQ = 08, T = 125 ns so CCR must be programmed with 0x28
PCLK1
(0x28 <=> 40d x 125 ns = 5000 ns.)
allowed value is 0x01
t = t + t
high r(SCL) w(SCLH)
t = t + t
low f(SCL) w(SCLL)
I2C communication speed, fSCL ~ 1/(thigh + tlow). The real frequency may differ due to
the analog noise filter input delay.
The CCR register must be configured only when the I
Inter-integrated circuit (I2C) interface
8 7 6 5
CCR[11:0]
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. See device datasheet for the definitions of parameters.
. See device datasheet for the definitions of parameters.
RM0033 Rev 9
4 3 2 1
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2
C is disabled (PE = 0).
0
rw
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