Figure 211. Block Diagram - ST STM32F207 Series Reference Manual

Advanced arm-based 32-bit mcus
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Hash processor (HASH)
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Figure 211. Block diagram

32-bit AHB2 bus
Control and status
registers
Interrupt registers
HASH_IMR
HASH_SR
Control register
HASH_CR
Start register
HASH_ST R
Context swapping
context
HASH_CSR0..50
Message digest
digest
HASH_H0...H4
RM0033 Rev 9
IN buffer
Data
register
HASH_DIN
write into HASH_DIN
or write DCAL bit to 1
or 1 complete block
transferred by the DMA
16 × 32-bit
IN FIFO
swa ppin g
IN FIFO full
or DCAL written to 1
SHA -1 / MD5
Hash / HMAC
processor core
RM0033
ai16081

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