Configuring The Spi In Master Mode; Figure 252. Ti Mode - Slave Mode, Continuous Transfer - ST STM32F207 Series Reference Manual

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Configuring the SPI in master mode

In the master configuration, the serial clock is generated on the SCK pin.

Select the BR[2:0] bits to define the serial clock baud rate (see SPI_CR1 register).

Select the CPOL and CPHA bits to define one of the four relationships between the

data transfer and the serial clock (see

TI mode is selected.

Set the DFF bit to define 8- or 16-bit data frame format

Configure the LSBFIRST bit in the SPI_CR1 register to define the frame format. This

step is not required when the TI mode is selected.

If the NSS pin is required in input mode, in hardware mode, connect the NSS pin to a

high-level signal during the complete byte transmit sequence. In NSS software mode,

set the SSM and SSI bits in the SPI_CR1 register. If the NSS pin is required in output

mode, the SSOE bit only should be set. This step is not required when the TI mode is

Set the FRF bit in SPI_CR2 to select the TI protocol for serial communications.

The MSTR and SPE bits must be set (they remain set only if the NSS pin is connected

to a high-level signal).

In this configuration the MOSI pin is a data output and the MISO pin is a data input.

Transmit sequence

The transmit sequence begins when a byte is written in the Tx Buffer.

The data byte is parallel-loaded into the shift register (from the internal bus) during the first

bit transmission and then shifted out serially to the MOSI pin MSB first or LSB first

depending on the LSBFIRST bit in the SPI_CR1 register. The TXE flag is set on the transfer

of data from the Tx Buffer to the shift register and an interrupt is generated if the TXEIE bit in

the SPI_CR2 register is set.

sampling trigger

250). This step is not required when the

RM0033 Rev 9

Serial peripheral interface (SPI)

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