Table 224. Document Revision History - ST STM32F207 Series Reference Manual

Revision history
34 Revision history
Date
06-Jul-2010
09-Dec-2010
1352/1381

Table 224. Document revision history

Version
1 Initial release.
Removed V
Updated Figure 1: System architecture
Updated Table 3: Number of wait states according to Cortex-M3
clock frequency. Updated embedded Flash memory organization in
Section 2.3.3; updated LATENCY bits in
control register (FLASH_ACR)
Section 2.3.5: Adaptive real-time memory accelerator (ART
Accelerator™).
Renamed FSMC NOR/SRAM 1/2 Bank1 into FSMC Bank1
NOR/PSRAM 1/2. Updated last two address ranges and added
Note 1 in Table 5: Memory mapping vs. Boot mode/physical
Power control (PWR)
Updated Figure 3: Power supply
Updated V
REF
supply and reference
Section 4.2.2: Brownout reset
Reset and clock controller
Changed HSE oscillator frequency to 4-26 MHz and replaced
SPI2S_CKIN by I2S2_CKIN/I2S3_CKIN in
Added note related to RTC_TR register read in
RTC/AWU clock.
2
Extended PLL input frequency to 2 MHz, and updated caution note
related to PLLM[5:0] bit in
register (RCC_PLLCFGR).
System configuration controller
Added Section 7.1: I/O compensation cell
configuration controller
Added case of FSMC remapped at address 0x0000 0000, and
updated description of SYSCFG_MEMRMP register and
MEM_MODE bit in
(SYSCFG_MEMRMP).
Removed not related to READY bit in
cell control register
ADC
Updated V
DDA
Updated Section 10.2: ADC main
Updated Section 10.3.2: ADC
Changed PCLK to PCLK2 for ADCPRE bit description in
Section 10.13.16: ADC common control register
Updated JSQ bit description, and added note in
ADC injected sequence register
RM0033 Rev 9
Changes
from the whole document.
DDSA
to support up to 7 wait states; added
overview.
range in Section 4.1.1: Independent A/D converter
voltage; BOR default status updated in
(BOR).
Section 5.3.2: RCC PLL configuration
(SYSCFG).
Section 7.2.1: SYSCFG memory remap register
(SYSCFG_CMPCR).
low-speed and V
REF
features.
clock.
(ADC_JSQR).
RM0033
for FSMC Static MemCtl.
Section : Flash access
Figure 9: Clock tree.
Section 5.2.8:
in Section 7: System
Section 7.2.7: Compensation
ranges in Table 32: ADC pins
(ADC_CCR).
Section 10.13.12:
remap.