Slowing Down System Clocks; Peripheral Clock Gating; Table 7. Low-Power Mode Summary - ST STM32F205 series Reference Manual

Power control (PWR)
Mode name Entry
WFI or Return
Sleep
from ISR
(Sleep now or
Sleep-on-exit)
WFE
PDDS and LPDS
bits +
Stop SLEEPDEEP bit
+ WFI, Return
from ISR or WFE
PDDS bit +
SLEEPDEEP bit
Standby
+ WFI, Return
from ISR or WFE
4.3.1

Slowing down system clocks

In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be
reduced by programming the prescaler registers. These prescalers can also be used to slow
down peripherals before entering Sleep mode.
For more details refer to
4.3.2

Peripheral clock gating

In Run mode, the HCLKx and PCLKx for individual peripherals and memories can be
stopped at any time to reduce power consumption.
To further reduce power consumption in Sleep mode the peripheral clocks can be disabled
prior to executing the WFI or WFE instructions.
Peripheral clock gating is controlled by the AHB1 peripheral clock enable register
(RCC_AHB1ENR), AHB2 peripheral clock enable register (RCC_AHB2ENR), AHB3
peripheral clock enable register (RCC_AHB3ENR) (see
register (RCC_APB1ENR)
(RCC_APB2ENR)).
Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting
the corresponding bit in RCC_AHBxLPENR and RCC_APBxLPENR registers.
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Table 7. Low-power mode summary

Wakeup
Any interrupt
Wakeup event
Any EXTI line (configured
in the EXTI registers,
internal and external lines)
WKUP pin rising edge,
RTC alarm (Alarm A or
Alarm B), RTC Wakeup
event, RTC tamper event,
RTC time stamp event,
external reset in NRST
pin, IWDG reset
Section 5.3.3: RCC clock configuration register
and RCC APB2 peripheral clock enable register
RM0033 Rev 8
Effect on
Effect on 1.2 V V
DD
domain clocks domain
clocks
CPU CLK OFF
no effect on other
None
clocks or analog
clock sources
HSI and
All 1.2 V domain HSE
clocks OFF oscillators
OFF
RCC APB1 peripheral clock enable
RM0033
Voltage regulator
ON
ON or in low- power
mode (depends on
PWR power control
register
(PWR_CR))
OFF
(RCC_CFGR).