Peripheral Sofs; Otg Low-Power Modes; Table 150. Compatibility Of Stm32 Low Power Modes With The Otg - ST STM32F207 Series Reference Manual

RM0033
is generated at any start of frame (SOF bit in OTH_FS_GINTSTS). The current frame
number and the time remaining until the next SOF are tracked in the host frame number
register (HFNUM).
An SOF pulse signal, generated at any SOF starting token and with a width of 20 HCLK
cycles, can be made available externally on the OTG_FS_SOF pin using the SOFOUTEN
bit in the global control and configuration register. The SOF pulse is also internally
connected to the input trigger of timer 2 (TIM2), so that the input capture feature, the output
compare feature and the timer can be triggered by the SOF pulse. The TIM2 connection is
enabled through the ITR1_RMP bits of TIM2_OR register.
29.7.2

Peripheral SOFs

In device mode, the start of frame interrupt is generated each time an SOF token is received
on the USB (SOF bit in OTH_FS_GINTSTS). The corresponding frame number can be read
from the device status register (FNSOF bit in OTG_FS_DSTS). An SOF pulse signal with a
width of 20 HCLK cycles is also generated and can be made available externally on the
OTG_FS_SOF pin by using the SOF output enable bit in the global control and configuration
register (SOFOUTEN bit in OTG_FS_GCCFG). The SOF pulse signal is also internally
connected to the TIM2 input trigger, so that the input capture feature, the output compare
feature and the timer can be triggered by the SOF pulse. The TIM2 connection is enabled
through the ITR1_RMP bits of the TIM2 option register (TIM2_OR).
The end of periodic frame interrupt (GINTSTS/EOPF) is used to notify the application when
80%, 85%, 90% or 95% of the time frame interval elapsed depending on the periodic frame
interval field in the device configuration register (PFIVL bit in OTG_FS_DCFG). This feature
can be used to determine if all of the isochronous traffic for that frame is complete.
29.8

OTG low-power modes

Table 150
Mode
Run
Sleep
Stop
Standby
1. Within Stop mode there are different possible settings. Some restrictions may also exist, please refer to
Section 4: Power control (PWR)
below defines the STM32 low power modes and their compatibility with the OTG.

Table 150. Compatibility of STM32 low power modes with the OTG

Description
MCU fully active
USB suspend exit causes the device to exit Sleep mode.
Peripheral registers content is kept.
USB suspend exit causes the device to exit Stop mode.
Peripheral registers content is kept
Powered-down. The peripheral must be reinitialized after
exiting Standby mode.
to understand which (if any) restrictions apply when using OTG.
USB on-the-go full-speed (OTG_FS)
(1)
.
RM0033 Rev 9
USB compatibility
Required when USB not in
suspend state.
Available while USB is in
suspend state.
Available while USB is in
suspend state.
Not compatible with USB
applications.
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