Fifo; Figure 27. Fifo Structure - ST STM32F207 Series Reference Manual

Advanced arm-based 32-bit mcus

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DMA controller (DMA)

FIFO

FIFO structure

The FIFO is used to temporarily store data coming from the source before transmitting them

to the destination.

Each stream has an independent 4-word FIFO and the threshold level is software-

configurable between 1/4, 1/2, 3/4 or full.

To enable the use of the FIFO threshold level, the direct mode must be disabled by setting

the DMDIS bit in the DMA_SxFCR register.

The structure of the FIFO differs depending on the source and destination data widths, and

is described in

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

Source: half-word

H7 H6 H5 H4 H3 H2 H1 H0

Source: half-word

H7 H6 H5 H4 H3 H2 H1 H0

Figure 27: FIFO

Source: byte

Source: byte

RM0033 Rev 9

Destination: word

W3, W2, W1, W0

Destination: half-word

H7, H6, H5, H4, H3, H2, H1, H0

Destination: word

W3, W2, W1, W0

Destination: byte

B15 B14 B13 B12 B11 B10 B9 B8

B7 B6 B5 B4 B3 B2 B1 B0

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