Table 14. Port Bit Configuration Table; Figure 13. Basic Structure Of A Five-Volt Tolerant I/O Port Bit - ST STM32F207 Series Reference Manual

RM0033
Each I/O port bit is freely programmable, however the I/O port registers have to be
accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR register is
to allow atomic read/modify accesses to any of the GPIO registers. In this way, there is no
risk of an IRQ occurring between the read and the modify access.
Figure 13
port bit configurations.
To on-chip
peripheral
Read
Write
Read/write
From on-chip
peripheral
1. V
DD_FT
MODER(i)
[1:0]
01
shows the basic structure of a 5 V tolerant I/O port bit.

Figure 13. Basic structure of a five-volt tolerant I/O port bit

Analog
Alternate function input
Alternate function output
is a potential specific to five-volt tolerant I/Os and different from V

Table 14. Port bit configuration table

OSPEEDR(i)
OTYPER(i)
0
0
0
0
SPEED
[B:A]
1
1
1
1
on/off
TTL Schmitt
trigger
Input driver
Output driver
Output
control
V
PUPDR(i)
[B:A] [1:0]
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
RM0033 Rev 9
General-purpose I/Os (GPIO)
Table 18 gives the possible
V
DD
on/off
V
DD on/off
down
P-MOS
V
SS
N-MOS
SS
Push-pull,
open-drain or
disabled
Analog
.
DD
(1)
I/O configuration
GP output
GP output
GP output
Reserved
GP output
GP output
GP output
Reserved (GP output OD)
(1)
V
DD_FT
Protection
diode
Pull
up
I/O pin
Protection
Pull
diode
V
SS
ai15939b
PP
PP + PU
PP + PD
OD
OD + PU
OD + PD
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