Reading The Calendar; Resetting The Rtc - ST STM32F207 Series Reference Manual

Real-time clock (RTC)
Programming the wakeup timer
The following sequence is required to configure or change the wakeup timer auto-reload
value (WUT[15:0] in RTC_WUTR):
1. Clear WUTE in RTC_CR to disable the wakeup timer.
2. Poll WUTWF until it is set in RTC_ISR to make sure the access to wakeup auto-reload
counter and to WUCKSEL[2:0] bits is allowed. It takes 1 to 2 RTCCLK clock cycles
(due to clock synchronization).
3. Program the wakeup auto-reload value WUT[15:0], and the wakeup clock selection
(WUCKSEL[2:0] bits in RTC_CR).Set WUTE in RTC_CR to enable the timer again.
The wakeup timer restarts down-counting. The WUTWF bit is cleared up to 2 RTCCLK
clocks cycles after WUTE is cleared, due to clock synchronization.
22.3.6

Reading the calendar

To read the RTC calendar registers (RTC_TR and RTC_DR) properly, the APB1 clock
frequency (f
frequency. This ensures a secure behavior of the synchronization mechanism.
If the APB1 clock frequency is less than seven times the RTC clock frequency, the software
must read the calendar time and date registers twice. If the second read of the RTC_TR
gives the same result as the first read, this ensures that the data is correct. Otherwise a third
read access must be done. In any case the APB1 clock frequency must never be lower than
the RTC clock frequency.
The RSF bit is set in RTC_ISR register each time the calendar registers are copied into the
RTC_TR and RTC_DR shadow registers. The copy is performed every two RTCCLK cycles.
To ensure consistency between the 2 values, reading RTC_TR locks the values in the
higher-order calendar shadow registers until RTC_DR is read. In case the software makes
read accesses to the calendar in a time interval smaller than 2 RTCCLK periods: RSF must
be cleared by software after the first calendar read, and then the software must wait until
RSF is set before reading again the RTC_TR and RTC_DR registers.
After waking up from low-power mode (Stop or Standby), RSF must be cleared by software.
The software must then wait until it is set again before reading the RTC_TR and RTC_DR
registers.
The RSF bit must be cleared after wakeup and not before entering low-power mode.
Note: After a system reset, the software must wait until RSF is set before reading the RTC_TR
and RTC_DR registers. Indeed, a system reset resets the shadow registers to their default
values.
After an initialization (refer to
software must wait until RSF is set before reading the RTC_TR and RTC_DR registers.
22.3.7

Resetting the RTC

The calendar shadow registers (RTC_TR and RTC_DR) and some bits of the RTC status
register (RTC_ISR) are reset to their default values by all available system reset sources.
On the contrary, the following registers are resetted to their default values by a backup
domain reset and are not affected by a system reset: the RTC current calendar registers,
the RTC control register (RTC_CR), the prescaler register (RTC_PRER), the RTC
calibration registers (RTC_CALIBR ), the RTC timestamp registers (RTC_TSTR and
RTC_TSDR), the RTC tamper and alternate function configuration register (RTC_TAFCR),
576/1381
) must be equal to or greater than seven times the f
PCLK1
Calendar initialization and configuration on page
RM0033 Rev 9
RM0033
RTC clock
RTCCLK
575): the