Timer Synchronization; Figure 152. Control Circuit In External Clock Mode 2 + Trigger Mode; Figure 153. Master/Slave Timer Example - ST STM32F207 Series Reference Manual

General-purpose timers (TIM2 to TIM5)
Counter clock = CK_CNT = CK_PSC
14.3.15

Timer synchronization

The TIMx timers are linked together internally for timer synchronization or chaining. When
one Timer is configured in Master mode, it can reset, start, stop or clock the counter of
another Timer configured in Slave mode.
Figure 153
blocks.
Note: The clock of the slave timer must be enabled prior to receiving events from the master timer,
and must not be changed on-the-fly while triggers are received from the master timer.
Using one timer as prescaler for another timer
Clock
408/1381

Figure 152. Control circuit in external clock mode 2 + trigger mode

TI1
CEN/CNT_EN
ETR
Counter register
TIF
presents an overview of the trigger selection and the master mode selection

Figure 153. Master/Slave timer example

TIM1
UEV
Master
mode
control
Prescaler Counter
34
TS
MMS
TRGO1 ITR0
Input trigger
selection
RM0033 Rev 9
35
TIM2
SMS
Slave
CK_PSC
mode
control
Prescaler
RM0033
36
MS33110V1
Counter
MS37387V1