I 2 S Master Mode - ST STM32F207 Series Reference Manual

Serial peripheral interface (SPI)
Table 100. Audio frequency precision (for PLLM VCO = 1 MHz or 2 MHz)
8000
16000
32000
48000
Disabled
96000
22050
44100
192000
8000
16000
32000
Enabled 48000
96000
22050
44100
1. This table gives only example values for different clock configurations. Other configurations allowing optimum clock
precision are possible.
2
25.4.4 I S master mode
2
The I S can be configured in master mode for transmission and reception. This means that
the serial clock is generated on the CK pin as well as the Word Select signal WS. Master
clock (MCK) may be output or not, thanks to the MCKOE bit in the SPI_I2SPR register.
Procedure
1. Select the I2SDIV[7:0] bits in the SPI_I2SPR register to define the serial clock baud
rate to reach the proper audio sample frequency. The ODD bit in the SPI_I2SPR
register also has to be defined.
2. Select the CKPOL bit to define the steady level for the communication clock. Set the
MCKOE bit in the SPI_I2SPR register if the master clock MCK needs to be provided to
the external DAC/ADC audio component (the I2SDIV and ODD values should be
718/1381
16-bit 192
32-bit 192
16-bit 192
32-bit 256
16-bit 256
32-bit 256
16-bit 192
32-bit 384
16-bit 384
32-bit 424
16-bit 290
32-bit 302
16-bit 302
32-bit 429
16-bit 424
32-bit 258
don't care 256
don't care 213
don't care 213
don't care 258
don't care 344
don't care 429
don't care 271
2 187
3 62
3 62
2 62
2 62
5 12
5 12
5 12
5 12
3 11
3 68
2 53
2 53
4 19
3 11
3 3
5 12
2 13
2 6
3 3
2 3
4 9
2 6
RM0033 Rev 9
(1)
1 8000
1 8000
1 16000
1 16000
1 32000
1 32000
1 48000
1 48000
1 96000
1 96014.49219
1 22049.87695
1 22050.23438
1 44100.46875
0 44099.50781
1 192028.9844
1 191964.2813
1 8000
0 16000.60059
1 32001.20117
1 47991.07031
1 95982.14063
1 22049.75391
0 44108.07422
RM0033
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0151%
0.0006%
0.0011%
0.0011%
0.0011%
0.0151%
0.0186%
0.0000%
0.0038%
0.0038%
0.0186%
0.0186%
0.0011%
0.0183%