Tim9/12 Counter (Timx_Cnt); Tim9/12 Prescaler (Timx_Psc); Tim9/12 Auto-Reload Register (Timx_Arr); Table 64. Output Control Bit For Standard Ocx Channels - ST STM32F207 Series Reference Manual

General-purpose timers (TIM9 to TIM14)
CCxE bit
0
1
Note: The states of the external I/O pins connected to the standard OCx channels depend on the
state of the OCx channel and on the GPIO registers.
15.4.9

TIM9/12 counter (TIMx_CNT)

Address offset: 0x24
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 CNT[15:0]: Counter value
15.4.10

TIM9/12 prescaler (TIMx_PSC)

Address offset: 0x28
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 PSC[15:0]: Prescaler value
15.4.11

TIM9/12 auto-reload register (TIMx_ARR)

Address offset: 0x2C
Reset value: 0xFFFF
15 14 13
rw rw rw
Bits 15:0 ARR[15:0]: Auto-reload value
470/1381

Table 64. Output control bit for standard OCx channels

Output disabled (OCx='0', OCx_EN='0')
OCx=OCxREF + Polarity, OCx_EN='1'
12 11 10 9
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12 11 10 9
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The counter clock frequency CK_CNT is equal to f
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in "reset mode").
12 11 10 9
rw rw rw rw
ARR is the value to be loaded into the actual auto-reload register.
Refer to the Section 15.3.1: Time-base unit
behavior.
The counter is blocked while the auto-reload value is null.
OCx output state
8 7 6
CNT[15:0]
rw rw rw
8 7 6
PSC[15:0]
rw rw rw
8 7 6
ARR[15:0]
rw rw rw
for more details about ARR update and
RM0033 Rev 9
5 4 3 2
rw rw rw rw
5 4 3 2
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/ (PSC[15:0] + 1).
CK_PSC
5 4 3 2
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RM0033
1 0
rw rw
1 0
rw rw
1 0
rw rw