Figure 69. Counter Timing Diagram, Internal Clock Divided By 2; Figure 70. Counter Timing Diagram, Internal Clock Divided By 4; Figure 71. Counter Timing Diagram, Internal Clock Divided By N - ST STM32F207 Series Reference Manual

RM0033

Figure 69. Counter timing diagram, internal clock divided by 2

CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)

Figure 70. Counter timing diagram, internal clock divided by 4

CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)

Figure 71. Counter timing diagram, internal clock divided by N

CK_PSC
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Advanced-control timers (TIM1 and TIM8)
0034 0035 0036
0035 0036
1F 20
RM0033 Rev 9
0000 0001 0002 0003
0000 0001
00
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MS31080V3
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