Host Channels - ST STM32F207 Series Reference Manual

USB on-the-go high-speed (OTG_HS)
stable again after the electrical debounce caused by the attachment of a pull-up resistor on
OTG_HS_FS_DP (full speed) or OTG_HS_FS_DM (low speed).
The application issues an USB reset (single-ended zero) via the USB by keeping the port
reset bit set in the Host port control and status register (PRST bit in OTG_HS_HPRT) for a
minimum of 10 ms and a maximum of 20 ms. The application monitors the time and then
clears the port reset bit.
Once the USB reset sequence has completed, the host port interrupt is triggered by the port
enable/disable change bit (PENCHNG bit in OTG_HS_HPRT) to inform the application that
the speed of the enumerated peripheral can be read from the port speed field in the host
port control and status register (PSPD bit in OTG_HS_HPRT), and that the host is starting
to drive SOFs (full speed) or keep-alive tokens (low speed). The host is then ready to
complete the peripheral enumeration by sending peripheral configuration commands.
Host suspend
The application can decide to suspend the USB activity by setting the port suspend bit in the
host port control and status register (PSUSP bit in OTG_HS_HPRT). The OTG_HS core
stops sending SOFs and enters the Suspended state.
The Suspended state can be exited on the remote device initiative (remote wakeup). In this
case the remote wakeup interrupt (WKUPINT bit in OTG_HS_GINTSTS) is generated upon
detection of a remote wakeup event, the port resume bit in the host port control and status
register (PRES bit in OTG_HS_HPRT) is set, and a resume signaling is automatically
issued on the USB. The application must monitor the resume window duration, and then
clear the port resume bit to exit the Suspended state and restart the SOF.
If the Suspended state is exited on the host initiative, the application must set the port
resume bit to start resume signaling on the host port, monitor the resume window duration
and then clear the port resume bit.
30.6.3

Host channels

The OTG_HS core instantiates 12 host channels. Each host channel supports an USB host
transfer (USB pipe). The host is not able to support more than 8 transfer requests
simultaneously. If more than 8 transfer requests are pending from the application, the host
controller driver (HCD) must re-allocate channels when they become available, that is, after
receiving the transfer completed and channel halted interrupts.
Each host channel can be configured to support IN/OUT and any type of
periodic/nonperiodic transaction. Each host channel has dedicated control (HCCHARx),
transfer configuration (HCTSIZx) and status/interrupt (HCINTx) registers with associated
mask (HCINTMSKx) registers.
1110/1381 RM0033 Rev 9
RM0033