Otg_Hs Programming Model; Core Initialization - ST STM32F207 Series Reference Manual

Advanced arm-based 32-bit mcus

Hide thumbs Also See for STM32F207 Series:

Table of Contents

USB on-the-go high-speed (OTG_HS)

Table 168. OTG_HS register map and reset values (continued)

OTG_HS programming model

The application must perform the core initialization sequence. If the cable is connected

during power-up, the current mode of operation bit in the Core interrupt register (CMOD bit

in OTG_HS_GINTSTS) reflects the mode. The OTG_HS controller enters host mode when

an "A" plug is connected or peripheral mode when a "B" plug is connected.

This section explains the initialization of the OTG_HS controller after power-on. The

application must follow the initialization sequence irrespective of host or peripheral mode

operation. All core global registers are initialized according to the core's configuration:

Section 2.3: Memory map

for the register boundary addresses.

RM0033 Rev 9

Table of Contents

Do you have a question about the STM32F207 Series and is the answer not in the manual?