Figure 344. Receive Dma Operation - ST STM32F207 Series Reference Manual

Ethernet (ETH): media access control (MAC) with DMA controller
The DMA does not acknowledge accepting the status until it has completed the time stamp
write-back and is ready to perform status write-back to the descriptor. If software has
enabled time stamping through CSR, when a valid time stamp value is not available for the
frame (for example, because the receive FIFO was full before the time stamp could be
written to it), the DMA writes all ones to RDES2 and RDES3. Otherwise (that is, if time
stamping is not enabled), RDES2 and RDES3 remain unchanged.
Set descriptor error
896/1381

Figure 344. Receive DMA operation

RxDMA suspended
Frame transfer
complete?
Yes Flush disabled ?
Flush the
remaining frame
Flush Own bit set
No
for next desc?
disabled ?
No
Yes Yes
Close RDES0 as
intermediate descriptor
Start RxDMA
(Re-)Fetch next
Poll demand /
descriptor
new frame available
(AHB)
error?
No
Yes
No Own bit set?
Yes
No
Frame data
available ?
Yes
No
Write data to buffer(s)
(AHB)
error?
No
Fetch next descriptor
(AHB)
error?
No
Frame transfer
No
complete?
Yes
Time stamp
present?
No
Close RDES0 as last
descriptor
(AHB)
error?
Yes
RM0033 Rev 9
Start Stop RxDMA
Yes
No
Wait for frame data
Yes
Yes
Write time stamp to
Yes
RDES2 & RDES3
(AHB)
No Yes
error?
No
RM0033
ai15643