Table 46. Positioning Of Captured Data Bytes In 32-Bit Words (8-Bit Width); Table 47. Positioning Of Captured Data Bytes In 32-Bit Words (10-Bit Width); Figure 58. Dcmi Signal Waveforms - ST STM32F205 series Reference Manual

RM0033
1. The capture edge of DCMI_PIXCLK is the falling edge, the active state of DCMI_HSYNC and
DCMI_VSYNC is 1.
1. DCMI_HSYNC and DCMI_VSYNC can change states at the same time.
8-bit data
When EDM[1:0] in DCMI_CR are programmed to "00" the interface captures 8 LSB's at its
input (D[0:7]) and stores them as 8-bit data. The D[13:8] inputs are ignored. In this case, to
capture a 32-bit word, the camera interface takes four pixel clock cycles.
The first captured data byte is placed in the LSB position in the 32-bit word and the 4
captured data byte is placed in the MSB position in the 32-bit word.
example of the positioning of captured data bytes in two 32-bit words.

Table 46. Positioning of captured data bytes in 32-bit words (8-bit width)

Byte address
0
4
10-bit data
When EDM[1:0] in DCMI_CR are programmed to "01", the camera interface captures 10-bit
data at its input D[0..9] and stores them as the 10 least significant bits of a 16-bit word. The
remaining most significant bits in the DCMI_DR register (bits 11 to 15) are cleared to zero.
So, in this case, a 32-bit data word is made up every two pixel clock cycles.
The first captured data are placed in the LSB position in the 32-bit word and the 2
captured data are placed in the MSB position in the 32-bit word as shown in

Table 47. Positioning of captured data bytes in 32-bit words (10-bit width)

Byte address
0
4

Figure 58. DCMI signal waveforms

DCMI_PIXCLK
DCMI_HSYNC
DCMI_VSYNC
31:24
D [7:0]
n+3
D [7:0]
n+7
31:26
0
0
RM0033 Rev 8
Digital camera interface (DCMI)
23:16
D [7:0] D
n+2
D [7:0] D
n+6
25:16
D [9:0]
n+1
D [9:0]
n+3
ai15606b
Table 46 gives an
15:8 7:0
[7:0] D [7:0]
n+1 n
[7:0] D
n+5 n+4
nd
Table 47.
15:10 9:0
0 D [9:0]
n
0 D
n+2
th
[7:0]
[9:0]
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