Read Interface; Relation Between Cpu Clock Frequency And Flash Memory Read Time; Table 3. Number Of Wait States According To Cpu Clock (Hclk) Frequency - ST STM32F205 Programming Manual

Flash memory interface
2.4

Read interface

2.4.1

Relation between CPU clock frequency and Flash memory read time

To correctly read data from Flash memory, the number of wait states (LATENCY) must be
correctly programmed in the Flash access control register (FLASH_ACR) according to the
frequency of the CPU clock (HCLK) and the supply voltage of the device.
correspondence between wait states and CPU clock frequency.
The prefetch must be disabled when the supply voltage is below 2.1 V.

Table 3. Number of wait states according to CPU clock (HCLK) frequency

Wait states (WS)
(LATENCY)
0 WS (1 CPU cycle)
1 WS (2 CPU cycles)
2 WS (3 CPU cycles)
3 WS (4 CPU cycles)
4 WS (5 CPU cycles)
5 WS (6 CPU cycles)
6 WS (7 CPU cycles)
7 WS (8 CPU cycles)
1. If IRROFF is set to VDD on STM32F20xx devices, this value can be lowered to 1.65 V when the device operates in a
reduced temperature range.
After reset, the CPU clock frequency is 16 MHz and 0 wait state (WS) is configured in the
FLASH_ACR register.
It is highly recommended to use the following software sequences to tune the number of
wait states needed to access the Flash memory with the CPU frequency.
Increasing the CPU frequency
1. Program the new number of wait states to the LATENCY bits in the FLASH_ACR
register
2. Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register
3. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register
4. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR
5. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are
taken into account by reading the clock source status (SWS bits) or/and the AHB
prescaler value (HPRE bits), respectively, in the RCC_CFGR register.
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Voltage range
2.7 V - 3.6 V
0 <HCLK≤ 30
30 <HCLK ≤ 60
60 <HCLK ≤ 90
90 <HCLK ≤ 120
96 < HCLK≤ 120
DocID15687 Rev 5
HCLK (MHz)
Voltage range Voltage range
2.4 V - 2.7 V
0 <HCLK ≤ 24 0 <HCLK ≤ 18
24 < HCLK≤ 48 18 <HCLK ≤ 36
48 < HCLK≤ 72 36 < HCLK≤ 54
54 <HCLK ≤ 72
72 < HCLK≤ 96
72 < HCLK≤ 90
90 < HCLK≤ 108
108 < HCLK≤ 120
Table 3
Voltage range
2.1 V - 2.4 V 1.8 V - 2.1 V
0 < HCLK ≤ 16
16 <HCLK ≤ 32
32 < HCLK≤ 48
48 < HCLK≤ 64
64 < HCLK≤ 80
80 < HCLK≤ 96
96 < HCLK≤ 112
112 < HCLK≤ 120
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