Cryp Dma Control Register (Cryp_Dmacr); Cryp Interrupt Mask Set/Clear Register (Cryp_Imscr) - ST STM32F207 Series Reference Manual

RM0033
19.6.5

CRYP DMA control register (CRYP_DMACR)

Address offset: 0x10
Reset value: 0x0000 0000
31 30 29
15 14 13
19.6.6

CRYP interrupt mask set/clear register (CRYP_IMSCR)

Address offset: 0x14
Reset value: 0x0000 0000
The CRYP_IMSCR register is the interrupt mask set or clear register. It is a read/write
register. On a read operation, this register gives the current value of the mask on the
relevant interrupt. Writing 1 to the particular bit sets the mask, enabling the interrupt to be
read. Writing 0 to this bit clears the corresponding mask. All the bits are cleared to 0 when
the peripheral is reset.
31 30 29
15 14 13
Bits 31:2 Reserved, must be kept at reset value
28 27 26 25
12 11 10 9
Reserved
Bits 31:2 Reserved, must be kept at reset value
Bit 1 DOEN: DMA output enable
0: DMA for outgoing data transfer is disabled
1: DMA for outgoing data transfer is enabled
Bit 0 DIEN: DMA input enable
0: DMA for incoming data transfer is disabled
1: DMA for incoming data transfer is enabled
28 27 26 25
12 11 10 9
Reserved
Bit 1 OUTIM: Output FIFO service interrupt mask
0: Output FIFO service interrupt is masked
1: Output FIFO service interrupt is not masked
Bit 0 INIM: Input FIFO service interrupt mask
0: Input FIFO service interrupt is masked
1: Input FIFO service interrupt is not masked
24 23 22
Reserved
8 7 6
24 23 22
Reserved
8 7 6
RM0033 Rev 9
Cryptographic processor (CRYP)
21 20 19 18
5 4 3 2
21 20 19 18
5 4 3 2
17 16
1 0
DOEN DIEN
rw rw
17 16
1 0
OUTIM INIM
rw rw
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